1. Field of the Invention
This invention relates to a memory-unit sense amplifier for memory for reading data from EEPROM or the like.
2. Description of the Related Art
FIG. 7 is a functional block diagram showing a microcomputer containing an EEPROM as a memory including a sense amplifier. In the drawing, numeral 100 indicates a microcomputer; numeral 1 indicates a CPU; numeral 2 indicates a mask ROM; numeral 3 indicates a RAM; numeral 4 indicates an EEPROM; numeral 5 indicates a sense amplifier of the EEPROM 4; numeral 6 indicates a bus; a numeral 7 indicates a terminal group comprising a power source terminal VDD, a ground terminal GND, a reset terminal RST, a clock terminal CLK, input/output terminal I/O, etc.
FIG. 8 is a circuit diagram showing a conventional sense amplifier. In the drawing, numerals 8, 9, 10, 11 and 12 indicate P-channel transistors (hereinafter referred to as "Pch"); and numerals 13, 14, 15, 16, 17 and 18 indicate N-channel transistors (hereinafter referred to as "Nch"). These transistors consist of MOSFETs. Numeral 19 indicates an inverter. Numerals 101 through 106 indicate signals, wirings, terminals, etc. in different parts of the circuit, of which numeral 101 indicates a wiring leading to a EEPROM memory cell; numeral 102 indicates a signal line which is set to "L" level when data is being read out; and numeral 106 indicates a terminal generating the output of this sense amplifier. Symbol VDD indicates a power source voltage.
FIG. 9 is a diagram showing the input/output characteristics of the conventional sense amplifier. The horizontal axis indicates memory cell current IE; and the vertical axis indicates output voltage Vout output from the output terminal 106.
FIGS. 10 and 11 are diagrams showing simulation results obtained with this sense amplifier, of which FIG. 10 shows signal changes in different parts of the circuit shown in FIG. 8 when there is a memory cell current IE, and FIG. 11 shows signal changes in these parts when there is no memory cell current IE. The horizontal axis indicates time, and the vertical axis indicates voltage.
Next, the operation of this prior-art example will be described. First, the basic operation of the microcomputer 100 with a built-in EEPROM will be described with reference to FIG. 7. The mask ROM 2 stores user programs for executing various functions necessary in using the microcomputer. The terminal group 7, comprising VDD, GND, RST, CLK, I/O, etc., is provided as terminals for connection to external apparatus. First, upon receiving a reset signal from the terminal RST, the CPU 1 executes a branch routine stored beforehand at a predetermined address in the ROM 2. In the branch routine, branch to a user mode is effected when an user mode execution command is received. In the user mode operation, data input from outside through the I/O terminal is received by the CPU 1 through the bus 6. The CPU 1 performs data processing in accordance with a user program stored in the mask ROM 2. Data needing temporary storage is stored in the RAM 3, and data needing constant storage, such as processing results, is stored in the EEPROM 4 serving as a data memory. The data stored in the EEPROM 4 is read out through the sense amplifier 5. Any data output to the exterior is outwardly transferred through the I/O terminal, etc.
Next, the operation of the conventional sense amplifier will be described with reference FIGS. 8, 10 and 11.
First, the case shown in FIG. 10, in which there is a memory cell current IE (the case in which the value of the memory cell data is at L level), will be described. When data in the EEPROM is read, an L-level input signal 102 is input to the gates of the Pch 8, 9 and 10 to cause the Pch 8, 9 and 10 to turn on, and the signal 103 attains H level. Then, the Nch 14 and 15 turn on, and a current starts to flow from the power source voltage VDD toward the memory cell through the wiring portions 104 and 105 to perform parasitic capacity charging on the wiring 101, which is connected to the bit line of the memory cell. At the same time, due to the presence of the memory cell current, the memory transistors (not shown) conduct. As a result, the gate of the Nch 13 is not charged, so that the Nch 13 does not turn on completely. Therefore, although the potential of the signal 103 becomes somewhat lower than that of the VDD, the Nch 14 and 15 do not turn off. Thus, the voltage of the signal 105 does not increase, and the Pch 11 and 12 turn on, the inverter 19 causing the output signal 106 to be at L level.
Next, the case shown in FIG. 11, where there is no memory cell current IE (the case where the value of the memory cell data is at H level), will be described. When data in the EEPROM is read out, an L-level input signal 102 is input to the gates of the Pch 8, 9 and 10 to cause the Pch 8, 9 and 10 to turn on, and the signal 103 attains H level. Then, the Nch 14 and 15 turn on, and a current starts to flow from the VDD toward the memory cell through the wiring portions 104 and 105 to perform parasitic capacity charging on the wiring 101. Further, due to the absence of a memory cell current, the memory transistors (not shown) are out of conduction. Thus, when the parasitic capacity charging has been completed, the gate of the Nch 13 is charged. Then, the Nch 13 turns on, and the voltage of the signal 103 is lowered to cause the Nch 14 and 15 to turn off. Thus, the voltage of the signal 105 is raised by the charging to cause the Nch 16 and 17 to turn on, and the inverter signal 19 causes an H level output signal 106 to be output. The Nch 18 is ON except when data is being read out, thereby keeping the signal 105 pulled down to L level.
In the conventional memory sense amplifier, constructed as described above, the memory cell current detection level of the sense amplifier is determined by the source/gate voltage of the Pch 10 (one of the transistors in the detection result output section), so that any fluctuations in the power source voltage VDD cause the source/gate voltage of the Pch to fluctuate correspondingly, resulting in great fluctuations being caused in the memory cell current detection level depending on the power source voltage, as shown in FIG. 9. The "memory cell current detection level" means the value of the memory cell current IE when the sense amplifier output Vout suddenly changes from the power source voltage level to the ground level. As shown in the drawing, this value increases as the power source voltage VDD increases.